News

IEEE2d
Precise Alignment in Ultra-Thin (< 1 µm) Interlayer Wafer-Level Active Device Transfer with SOI Temporary Bonding - IEEE Xplore
This study introduces a groundbreaking SOI-based temporary bonding technique for 3DIC, resolving significant challenges in thermal management and interlayer alignment. This platform can achieve ...
IEEE4d
4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration - IEEE Xplore
Different from Chip on Wafer stacking technology, Wafer on Wafer (WoW) stacking can provide a tighter pitch and higher interconnect density with higher through-put. The difficulty for WoW stacking is ...
Semiconductor Engineering5d
Novel Assembly Approaches For 3D Device Stacks
ECTC progress report on enabling technologies, including cooling chiplets, 1µm hybrid bonding, RDL buildups, and co-packaged ...